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  "presentationDate": "2023-05-01 00:00:00",
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      "text": "Cost\n3x\n$ Si IGBT SiC²",
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      "text": "Burn-in 5%\nYield Loss 25%\nSubstrate 40%\nSiC\nDevice Fab 20%\nEpitaxy 10%",
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      "text": "Typical Yield by Step¹\nSubstrate and Epitaxy Yield 65%\nDevice Fab – Wafer Yield (Scrap) 92%\nDevice Fab – Probe Yield 80%\nDicing Yield 98%\nPackaging Yield 99%\nFinal Test / Burn-in Yield 97%\nOverall Yield < 50%",
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      "text": "Reliability\nEscapes = f (yield, test coverage)³",
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      "text": "¹SiC yield and cost are typical values (2023), compiled from Yole, JP Morgan, PGC Consultants, KLA data, and other sources. Large variation from fab-to-fab.\n²At equivalent performance for EV traction inverter mission profile compared to comparable Si IGBT device.\n³See, for example, Williams-Brown or Seth-Agrawal test escape models",
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