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  "documentTitle": "Lasertec Corporation (6920)",
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      "text": "TSMC has to run parallel/redundant inspections as Lasertec's tool is unreliable",
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      "text": "Q: “What else have you heard about TSMC's feedback, whether through your connection or somebody else? I guess you said they're sort of struggling and making the transition. What are the reasons for that being? The optics or other problems?”\nA: “It's not so easy to change the process. If they have an established process and an established yield number of, let's say, 19% or something, phasing in the new technology should improve the yield. So, everything needs to be fine-tuned to surpass the existing solution. And that's not so easy with a new technology like actinic inspection. It's going to take time, so they will have to run parallel inspections of the same masks, every day, just to make sure that they get the same results...”\nQ: “So, whenever they do use a Lasertec machine, they're having to kind of duplicate the inspection with other machines?”\nA: “Yes. Just to make sure there are no defects that go through without detection. If that happens, the same defect will print on every single semiconductor. And if it's a fatal defect, it can cost them billions. They cannot ship any wafers anymore.” - Longtime, senior semicap equipment executive in Japan who is friendly with Lasertec's CEO",
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      "text": "Lasertec’s actinic EUV tool is so defective and unreliable that TSMC, Intel, and Samsung have all substituted non-EUV alternatives for inspecting EUV masks, improvising with KLA’s legacy Teron DUV tool plus electron beam inspection - indicating that actinic EUV is useful but not essential, nor worth $50MM per tool. Industry sources further told us that all three of Lasertec’s key customers have quietly built their own mask inspection systems as a workaround, using a very low power EUV source called High Harmonic Generation (HHG). One source close to these customers stated his surprise at learning that they were actually using Lasertec’s old DUV tool while claiming they were using their EUV machine - we suspect Intel, whose EUV mask team we think is engaging in a face-saving cover-up, given their massive bet on Lasertec. A Japanese semiconductor executive close to both TSMC and Lasertec stated that TSMC is running parallel, redundant inspections with non-EUV tools: “...parallel inspections of the same masks...just to make sure there are no defects.”",
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